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Espressif Systems /ESP32-S2 /APB_SARADC /THRES_CTRL

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Interpret as THRES_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN 0 (ADC2_THRES_MODE)ADC2_THRES_MODE 0 (ADC1_THRES_MODE)ADC1_THRES_MODE 0ADC2_THRES0ADC1_THRES0 (ADC2_THRES_EN)ADC2_THRES_EN 0 (ADC1_THRES_EN)ADC1_THRES_EN

Description

Configure monitor threshold for DIG ADC2

Fields

CLK_EN

Clock gate enable.
ADC2_THRES_MODE

1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt.
ADC1_THRES_MODE

1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt.
ADC2_THRES

ADC2 threshold.
ADC1_THRES

ADC1 threshold.
ADC2_THRES_EN

Enable ADC2 threshold monitor.
ADC1_THRES_EN

Enable ADC1 threshold monitor.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data